Flash memories are commonly applicable to mass storage subsystems for electronic devices employed in mobile communications, game sets, and so forth. Such subsystems are usually implemented as either removable memory cards that can be inserted into multiple host systems or as non-movable embedded storage within the host systems. In both implementations, the subsystem includes one or more flash devices and often a subsystem controller.
Flash memories are composed of one or more arrays of transistor cells, each cell capable of non-volatile storage of one or more bits of data. Therefore, flash memories do not require power to retain the data programmed therein. Once programmed however, a cell must be erased before it can be reprogrammed with a new data value. These arrays of cells are partitioned into groups to provide for efficient implementation of read, program and erase functions. The typical flash memory architecture for mass storage arranges large groups of cells into erasable blocks. Each block is further partitioned into one or more addressable sectors that are the basic unit for read and program functions.
Flash memories basically have their own functional operations of reading, writing (or programming), and erasing. Flash memories additionally extend their facilities to practice a page copy operation (or a copy-back operation). The page copy operation is to transcript data stored in a page assigned to a specific address to another page assigned to another address. During the page copy, data stored in a page of a specific address are transferred to a page buffer and then the data remaining in the page buffer are written into another page assigned to another address by way of a programming process without reading the data out of the flash memory. The page copy function eliminates a need of reading-out data to be written and of loading data to be written from the external source of the flash memory, which is advantageous to enhancing systemic data rates associated with the subsystem controller.
However, unfortunately, it may occur that the pages to be copied and to be written have their own error bits. As shown in FIG. 1, assuming that a page PG4 is to be copied and a page PGn-3 is to be written, both pages each having one error bit, the data stored in the page PG4 is transferred to the page buffer 10 and then written into the page PGn-3 from the page buffer 10. As a result of the page copy operation, two error bits are included in the page PGn-3. Because most flash memory controllers used as subsystem controllers in a card-type memory are usually only designed to correct one-bit error for a page, such a two-bit error in a page may be incapable of being cured after completing the copy back operation.
Although a flash memory controller could be equipped with an error correcting function capable of coping even with the two-bit error per page, it would cause the circuit architecture to be much more complex and thereby deteriorate operational efficiencies in the memory control system.
Embodiments of the invention address these and other limitations of the prior art.